Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node
Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node
(Third Party Funds Group – Sub project)
Overall project: Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7nm Node
Project leader:
Project members:
Start date: 1. January 2016
End date: 31. December 2018
Acronym: SUPERAID7
Funding source: EU - 8. Rahmenprogramm - Horizon 2020, Leadership in Enabling & Industrial Technologies (LEIT)
URL: https://www.superaid7.eu
Abstract
Among the physical limitations which challenge progress in nanoelectronics for ag-gressively scaled More Moore, process variability is getting ever more critical. Effects from various sources of process variations, both systematic and stochastic, influence each other and lead to variations of the electrical, thermal and mechanical behavior of devices, interconnects and circuits. Correlations are of key importance because they drastically affect the percentage of products which meet the specifications. Whereas the comprehensive experimental investigation of these effects is largely impossible, modelling and simulation (TCAD) offers the unique possibility to predefine process variations and trace their effects on subsequent process steps and on devices and circuits fabricated, just by changing the corresponding input data. This important requirement for and capability of simulation is among others highlighted in the International Technology Roadmap for Semiconductors ITRS.
SUPERAID7 will build upon the successful FP7 project SUPERTHEME which fo-cused on advanced More-than-Moore devices, and will establish a software system for the simulation of the impact of systematic and statistical process variations on advanced More Moore devices and circuits down to the 7 nm node and below, includ-ing especially interconnects. This will need improved physical models and extended compact models. Device architectures addressed in the benchmarks include espe-cially TriGate/ωGate FETs and stacked nanowires, including alternative channel ma-terials. The software developed will be benchmarked utilizing background and side-ground experiments of the partner CEA. Main channels for exploitation will be soft-ware commercialization via the partner GSS and support of device architecture activi-ties at CEA. The Chair of Electron Devices contributes to the development of an inte-grated three-dimensional topography simulator extending background tools from Fraunhofer IISB and TU Wien.