Charge compensation in 4H silicon carbide – Simulation, modelling and experimental verification

Charge compensation in 4H silicon carbide - Simulation, modelling and experimental verification

(Third Party Funds Single)

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Start date: 1. April 2016
End date: 14. April 2019
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Funding source: DFG-Einzelförderung / Sachbeihilfe (EIN-SBH)
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Abstract

For power semiconductor devices in silicon, device patterns with charge compensation between adjacent p- and n-doped semiconductor regions are applied. These patterns enable the realization of unipolar devices with blocking voltage under blocking operation and low device resistance in forward conduction. First semiconductor devices fabricated in silicon carbide employing charge compensation patterns are following design rules that are either based on theoretical calculations which are based on the well-controlled silicon technology or using non-empiric trial-and-error methods. Hereby, a suitable design of the compensation patterns is achieved either with a poor degree of compensation at all or only by repetitive process variations.This proposal is aiming to provide the foundation for the realization of charge compensation patterns with a high degree of compensation, and to conduct a systematic investigation regarding their electrical characteristics and the impact of physical effects. In particular, the impact of incomplete activation and ionization of dopants in SiC as well as the surface passivation on the degree of compensation, the breakdown voltage and the drift resistance is investigated. This allows for an improvement of existing simulation models for higher accuracy and the derivation of an analytical description of these charge compensation patterns that are not (as in silicon) based on a fully controlled semiconductor technology.With the aid of analytical modelling based on charge compensation patterns in silicon as a starting point and considering incomplete activation of dopants, both modelling and two dimensional TCAD simulations for lateral charge compensation patterns in silicon carbide will be implemented. The fabrication of lateral test patterns corresponding to the simulations and their electric characterization are used to increase the modelling accuracy and extension of the underlying models based on the measurement results. These models are then used to transfer and verify the results to lateral power transistors in SiC. Additionally, dynamic switching experiments will be carried out to evaluate the impact of physical effects like incomplete ionisation on electrical properties (e.g. avalanche breakdown) in charge compensation patterns. Finally, vertical charge compensation patterns will be realized to validate the methodology of this scientific approach as a whole.The results from this research project will simplify the fabrication of lateral and vertical power semiconductor devices on 4H-SiC by provision of accurate physical models for charge compensation.

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